VHDL MCQ Quiz Hub

1. In which part of the VHDL code, components must be declared?
Library
Entity
Architecture
Configuration

2. Which of the following function is used to map the component?
COMPONENT INSTANTIATE
PORT MAP
GENERIC MAP
USE

3. How many ways are there in VHDL to map the components?
1
2
3
4

4. What is the property of Positional mapping?
Easier to write
Less error prone
Ports can be left unconnected
Difficult to write

5. __________ mapping is less error prone.
Port
Positional
Nominal
Generic

6. A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
LABEL : my_component PORT MAP (l, m, n);
LABEL : my_component PORT MAP (y, a);
LABEL : my_component PORT MAP (l => a, m => b, n => y);
LABEL : my_component PORT MAP(a, b, y>= a);

7. Which of the following is the right way to leave a port unconnected?
L1 : my_component PORT MAP(a); a <= OPEN;
L1 : my_component PORT MAP(a := OPEN);
L1: my_component PORT MAP(a => OPEN);
L1 : my_component PORT MAP(a); a := OPEN;

8. How to declare a 2 input OR gate in the structural modeling?
COMPONENT or IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;
COMPONENT or IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;
COMPONENT or_gate IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;
COMPONENT or_gate IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;

9. Which of the following is the correct order for a structural model in VHDL?
Libraries, Entity declaration, Component declaration, Component instantiation
Libraries, Component declaration, Entity declaration, Component instantiation
Libraries, Entity declaration, Component instantiation, Component declaration
Component declaration, Libraries, Entity declaration, Component instantiation

10. Refer to the model given below, which circuit is designed? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY design IS PORT(a, b, c : in BIT; x, y : out BIT); END design; ARCHITECTURE arch1 OF design IS COMPONENT xor2 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT and2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT or2 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: xor2 PORT MAP(a, b, s1); X2 : xor2 PORT MAP(s1, c, x); X3: and2 PORT MAP(a, b, s2); X4 : and2 PORT MAP(a, c, s3); X5: and2 PORT MAP(b, c, s4); X6: or2 PORT MAP(s2, s3, s5); X7: or2 PORT MAP(s4, s5, y); END arch1;
Half adder
Comparator 2- bits
Full adder
Can’t be determined